Add NEON SIMD path for CPU Adam on AArch64
The CPU Adam kernel ran scalar on AArch64 machines without SVE, which
includes every Apple Silicon Mac (the ZeRO-Offload optimizer path on
that platform). simd.h gains a 4-lane NEON implementation of the
existing SIMD macro set, following the AVX512 semantics: fp16 through
the hardware converters, bf16 through the same round-to-nearest-even
with nan-quieting flow as store_16_f32_as_bf16_nearest, and x86
andnot's operand order preserved. Step_AVX's non-AVX512 bf16 bailout
is lifted for NEON since the bf16 converters exist there.
Builders: simd_width() advertises -D__NEON__ for AArch64 without SVE
(the vdivq/vsqrtq intrinsics used are A64-only, so 32-bit ARM keeps
the scalar path) and the MPS cpu_adam builder switches from
-D__SCALAR__ accordingly. Lion/Adagrad gates are left untouched and
keep their scalar behavior.
Measured on an M5 Max (macOS 26.3, clang, libomp), DeepSpeedCPUAdam
step on 50M params, 10-step average, vs the -D__SCALAR__ build:
fp32 11.5 -> 3.8 ms, fp16 11.5 -> 3.3 ms, bf16 12.7 -> 4.9 ms.
NEON and scalar builds produce bit-identical fp16 results on identical
inputs; all dtypes match a fp32 torch.optim oracle within storage
rounding, including sizes exercising the SIMD/scalar tail boundary.
Signed-off-by: PKUWZP <zhipeng.rainbowserie@gmail.com>
