llvm

55587f7b - [CodeGen] Mark read_register of allocatable physreg as live-in (#200825)

[CodeGen] Mark read_register of allocatable physreg as live-in (#200825) llvm.read_register / llvm.read_volatile_register of an allocatable register (e.g. the MSVC __getReg/__getRegFp intrinsics reading xN/dN) was lowered to a plain COPY from the physical register. That COPY uses a physical register that is never defined, which the machine verifier rejects as "Using an undefined physical register" (seen on read-fp-reg.ll under LLVM_ENABLE_EXPENSIVE_CHECKS). Reading such a register only makes sense as "whatever value it currently holds", i.e. like an inline-asm read; it cannot be modelled as a normal SSA use of a physical register, and a live-in only works in the entry block. Lower these reads in AArch64 like the existing MRS/MSR sysreg path: select to a small pseudo (READ_REGISTER_GPR64 / READ_REGISTER_FPR64) that carries the source register as an immediate operand rather than a tracked physical-register use, and have the AsmPrinter materialize the real "mov Xt, Xn" / "fmov Dt, Dn". The verifier never sees an undefined physreg use, so the read is valid in any block and needs no live-in or undef. Reads of reserved registers (e.g. sp) and system registers keep their existing lowering.