llvm-project

00e6eca2 - [AArch64] Fix assertion failure during promotion of EXTEND_VECTOR_INREG. (#171619)

[AArch64] Fix assertion failure during promotion of EXTEND_VECTOR_INREG. (#171619) This fixes an assertion failure in `SelectionDAG::getNode` on AArch64 during Type Legalization. The crash is triggered by an `ANY_EXTEND_VECTOR_INREG` operation involving small vector types (e.g., v16i1). The crash occurs when the Type Legalizer processes a vector extend operation where the input vector uses small elements, specifically in the case of a ShuffleVector that generates a mask vector. 1. **Original Node**: `any_extend_vector_inreg (v16i1) -> v2i16`. (This is physically valid: 16 bits < 32 bits). 2. **Promotion Issue**: When both the input and result types are promoted for legality: * The **Result** (`v2i16`) is promoted to a larger legal type, e.g., `v2i32` (**64 bits**). * The **Input** (`v16i1`) is promoted to `v16i8` (**128 bits**) due to the necessary scalar promotion of `i1` to `i8`. 3. The legalizer then attempts to create the new node: `any_extend_vector_inreg (v16i8) -> v2i32`. 4. Since $128 \text{ bits} > 64 \text{ bits}$, the physical constraint of the `EXTEND_VECTOR_INREG` operation is violated, causing the assertion to fail. ### Solution In `DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG`, when the size of the promoted input vector (`Promoted`) is found to be greater than the size of the promoted result vector (`NVT`): We explicitly truncates the promoted input to the size of the result type (`NVT`), ensuring the final `*_EXTEND_VECTOR_INREG` node satisfies the size constraint before it is created. This behavior aligns with the fact that `*_EXTEND_VECTOR_INREG` typically only requires the low-order lanes of the input vector. **Test Added**: `llvm/test/CodeGen/AArch64/issue-171032.ll` Fixes: #171032