llvm-project

06411399 - [AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987)

[AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987) Added a srl pattern for true16 flow. Changing right shift 16bit to a reg_sequence `srl vgpr32, 16 -> reg_sequence (vgpr32.hi16, 0)` and finally it's lowered to two COPY `vdst.lo16 = COPY vsrc.hi16` `vdst.hi16 = COPY 0` The benefits of this transform is allowing the following pass to optimize out these copy.