llvm-project

0d51fec3 - [NVPTX] PerformSELECTShiftCombine drops high bits of a wide guarded shift amount (#201165)

[NVPTX] PerformSELECTShiftCombine drops high bits of a wide guarded shift amount (#201165) LLVM shifts produce poison if you shift greater than the width of the operand. But PTX shifts clamp the shift amount: > shl/shr: Shift amounts greater than the register width N are clamped > to N. NVPTXISelLowering looks for shl/shr which guard against an out-of-range shift and lower these to an unguarded PTX shift: define i64 @f(i64 %x, i64 %shift) { %cmp = icmp ult i64 %shift, 64 %shl = shl i64 %x, %shift %sel = select i1 %cmp, i64 %shl, i64 0 ret i64 %sel } In PTX shifts the shift amount is always i32, whereas in LLVM the shift amount is the same type as the "shiftee". Therefore in the i64 case, this lowering is only sound if we know that the upper 32 bits of the shift amount are all zero.