llvm-project

1669bd3a - [RISCV] Accept c.slli/c.srli/c.srli with a 0 immediate as hints. (#150689)

[RISCV] Accept c.slli/c.srli/c.srli with a 0 immediate as hints. (#150689) These encodings were previously assigned to c.slli64/srli64/srai64, and designated as hints for RV32 and RV64. Those mnemonics no longer appear in the ISA manual after RV128 was removed. The spec now says that c.slli/c.srli/c.srai with an immediate of 0 is a hint. This patch updates the assembler to accept this. I've left the old spelling for backwards compatibility but we disassemble a shift with a zero immediate. The C_SLLI64_HINT/C_SRLI_HINT/C_SRAI_HINT instructions are removed and the predicates for C_SLLI/C_SRLI/C_SRAI not accept a 0 immediate. Fixes #150304