llvm-project

17bfd213 - [AArch64] Add assembly/disassembly for multi-vector AES instructions (#113307)

[AArch64] Add assembly/disassembly for multi-vector AES instructions (#113307) This patch adds assembly/disassembly for the following multi-vector SVE instructions - AESE (two/four registers) - AESD (two/four registers) - AESDIMC (two/four registers) - AESEMC (two/four registers) - Introduce assembler extension tests for the new Armv9.6 sve-aes2 and ssve-aes features - In accordance with: https://developer.arm.com/documentation/ddi0602/latest/