llvm-project

2bce962d - [clang][RISCV] Add big-endian RISC-V target support (#165599)

[clang][RISCV] Add big-endian RISC-V target support (#165599) We proceeded with frontend/clang changes, until we figure out how ABI for BE should look like. Once it is final, we will proceed with codegen changes. In this patch several things addressed: - Define riscv32be/riscv64be target triples - Set correct data layout for BE targets - Handle BE-specific ABI details - Emit warning for BE case since it is still experimental