[RISCV] Add regalloc hints for BSETI/BEXTI (#173964)
This patch hints the register allocator to use the same source and
destination registers for the `BEXTI/BSETI` instructions when the
`Xqcibm` vendor extension is enabled. This enables the generation of the
compressed `QC_C_BEXTI/QC_C_BSETI` instructions when possible.
