llvm-project

2f436590 - [ARM] Add tablegen patterns for vsdot and vudot high index. (#174728)

[ARM] Add tablegen patterns for vsdot and vudot high index. (#174728) The index on a vsdot and vudot instruction can be 0/1 from a D-reg, not 0/1/2/3 from a Q reg as would be expected. Add a pattern to allow extracting from the high half of the input vector. Fixes #174688