llvm-project

32913724 - [mlir][vector] Fix 0-d vector transfer mask inference (#116526)

[mlir][vector] Fix 0-d vector transfer mask inference (#116526) When inferring the mask of a transfer operation that results in a single `i1` element, we could represent it using either `vector<i1>` or vector<1xi1>. To avoid type mismatches, this PR updates the mask inference logic to consistently generate `vector<1xi1>` for these cases. We can enable 0-D masks if they are needed in the future. See: https://github.com/llvm/llvm-project/issues/116197