llvm-project

343e3c6b - [LLVM][CodeGen][SVE] Make bf16 fabs/fneg isel consistent with fp16. (#147543)

[LLVM][CodeGen][SVE] Make bf16 fabs/fneg isel consistent with fp16. (#147543) Whilst at first glance there appears to be no native bfloat instructions to modify the sign bit, this is only the case when FEAT_AFP is implemented. Without this feature vector FABS/FNEG does not care about the floating point format beyond needing to know the position of the sign bit. From what I can see LLVM has no support for FEAT_AFP in terms of feature detection or ACLE builtins and so I believe the compiler can work under the assumption the feature is not enabled. In fact, if FEAT_AFP is enabled then I believe the current isel is likely broken for half, float and double anyway.