llvm-project

3b3d6e87 - [X86] Ignore debug instructions when choosing LVI graph leaders (#224496)

[X86] Ignore debug instructions when choosing LVI graph leaders (#224496) X86 LVI load hardening used the raw first `MachineInstr` in each block as its gadget-graph representative. A leading debug instruction could therefore add a structural graph vertex, change the greedy cut cost, and relocate an `LFENCE` between ordinary loads. Choose the first non-debug instruction instead. Keep pseudo probes eligible by passing `SkipPseudoOp=false`, and naturally omit a vertex for a debug-only block. Add an LLVM IR regression test comparing debug and strip-debug code generation. Fixes #224484 AI disclosure: This patch was developed with OpenAI Codex 5.6 Sol and co-reviewed by Claude and Yongqiang Tian.