llvm-project

3be7b2fc - [X86] Improve handling of i512 SHL(-1,Amt) + SRL(-1,Amt) "mask shifts" (#186806)

[X86] Improve handling of i512 SHL(-1,Amt) + SRL(-1,Amt) "mask shifts" (#186806) An extension of the existing one-bit shift patterns - perform an initial select to handle 'allones/allzeros' elements and then insert the element that has a partial mask on top of it. Often turns up in bit manipulation patterns