llvm-project

47b756a5 - [RISCV] Only reduce VLs of instructions with demanded VLs (#168693)

[RISCV] Only reduce VLs of instructions with demanded VLs (#168693) In RISCVVLOptimizer we first compute all the demanded VLs, then we walk backwards through the function and try to reduce any VLs. We don't actually need to walk backwards anymore since after #124530 the order in which we modify the instructions doesn't matter. This patch changes it to just iterate over the instructions with a demanded VL computed, which means we don't iterate over scalar instructions etc. This also fixes #168665, where we triggered an assert on instructions with a dead $vxsat implicit-def: dead %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat Because $vxsat is a reserved register, DeadMachineInstructionElim won't remove it and the instruction makes it to RISCVVLOptimizer. And because the def of %x is dead, we don't reach this instruction in the dataflow analysis. This instruction returns true for isCandidate, so we would try to lookup its demanded VL which doesn't exist and assert. But with this patch we don't try to reduce instructions that aren't in DemandedVLs, which fixes the crash.