llvm-project

47f32bdd - [VectorCombine] Fold reduction chains with equivalent bitcast sources (#212084)

[VectorCombine] Fold reduction chains with equivalent bitcast sources (#212084) ## Description `foldShuffleChainsToReduce` currently identifies leaf sources by SSA value identity. This can prevent a shuffle reduction chain from being folded when multiple bitcast instructions represent the same vector source. This happens when an earlier VectorCombine transform moves a bitcast through a shuffle and creates a new bitcast of the same underlying value. The reduction matcher then sees the original and newly created bitcasts as separate sources and rejects the fold. This PR treats bitcast sources as equivalent when they have the same result type and the same operand. It then merges the demanded lanes of equivalent sources while preserving duplicate-lane semantics: * Reject duplicate or overlapping lanes for non-idempotent reductions. * Allow overlapping lanes for idempotent reductions. * Continue to reject sources with different underlying values or result types. This allows the default optimization pipeline to recognize and fold the horizontal reductions in both `hsum_i32_4` and `hsum_i32_8` in #210897 ## Tests * Add VectorCombine tests for: * equivalent bitcast sources with disjoint demanded lanes; * overlapping lanes for non-idempotent reductions; * duplicates within a later equivalent source; * bitcasts of different underlying values; * overlapping lanes for idempotent reductions. Fixes #210897.