llvm-project

4eac5766 - [RISCV] Add scheduler definitions for SpacemiT-X60 (#137343)

[RISCV] Add scheduler definitions for SpacemiT-X60 (#137343) This patch adds an initial scheduler model for the SpacemiT-X60, including latency for scalar instructions only. The scheduler is based on the documented characteristics of the C908, which the SpacemiT-X60 is believed to be based on, and provides the expected latency for several instructions. I ran a probe to confirm all of these values and to get the latency of instructions not provided by the C908 documentation (e.g., double floating-point instructions). For load and store instructions, the C908 documentation says the latency is \>= 3 for load and 1 for store. I tried a few combinations of values until I got the current values of 5 and 3, which yield the best results. Although the X60 does appear to support multiple issue for at least some floating point instructions, this model assumes single issue as increasing it reduces the gains below. This patch gives a geomean improvement of ~4% on SPEC CPU 2017 for both rva22u64 and rva22u64_v, with some benchmarks improving up to 18% (508.namd_r). There were a couple of execution time regressions, but only in noisy benchmarks (523.xalancbmk_r and 510.parest_r). * rva22u64: https://lnt.lukelau.me/db_default/v4/nts/507?compare_to=405 (compares a55f7275 to the baseline 8286b804) * rva22u64_v: https://lnt.lukelau.me/db_default/v4/nts/474?compare_to=404 (compares a55f7275 to the baseline 8286b804) This initial scheduling model is strongly focused on providing sufficient definitions to provide improved performance for the SpacemiT-X60. Further incremental gains may be possible through a much more detailed microarchitectural analysis, but that is left to future work. Further scheduling definitions for RVV can be added in a future PR.