llvm-project

4f18f3f0 - [RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)

[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635) We prefer to emit addi instead of ori because its more compressible, but this can pessimize the sext.w removal pass. If the input to the OR is known to be a sign extended 32 bit value, we can use addiw instead of addi which will give more power to the sext.w removal pass. As it is known to produce sign a sign extended value and only consume the lower 32 bits. Fixes #128468.