llvm-project

4fe326dd - [X86] combineVECREDUCE_LOGIC - add missing reduce_xor parity result sign extension (#217002)

[X86] combineVECREDUCE_LOGIC - add missing reduce_xor parity result sign extension (#217002) #199544 enabled support for reduce_xor with non-vXi1 types, but we were missing the sign extension that was handled only for the reduce_or/and cases Fixes #215069