llvm-project

536fe74a - [RISCV] Modify register type of extd* Xqcibm instructions (#134027)

[RISCV] Modify register type of extd* Xqcibm instructions (#134027) The v0.8 spec specifies that rs1 cannot be x31 (t6) since these instructions operate on a pair of registers (rs1 and rs1 + 1) with no wrap around. The latest spec can be found here: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.8.0