llvm-project

58df9b1a - [RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)

[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693) This block of code is currently conditional on the fusions being enabled but as far as I can tell, does no harm to generally enable. The net effect is the generically compiled code runs slightly better on machines with this fusion. The actual motivation is merely to stop confusing myself when I see the sequence in code; the register allocators choice to sometimes blow two registers instead of one is just generally weird, and my eyes spot it when scanning disassembly. (Note that this is just the regalloc hint; the scheduling changes remain conditional, and probably should remain so.)