llvm-project

5a53fce8 - [RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)

[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657) This PR addresses post-commit reviews in #182416 Previously, `RISCVMoveMerger` only identified and merged 32-bit moves into a 64-bit GPRPair move if the even-indexed register most appeared before the odd-index register move. This patch extends the pass by disregarding the order of even/odd-index pair.