llvm-project

667ba7f8 - [AMDGPU] Fix GCNRewritePartialRegUses pass: vector regclass is selected instead of scalar. (#69957)

[AMDGPU] Fix GCNRewritePartialRegUses pass: vector regclass is selected instead of scalar. (#69957) For the following testcase: undef %1.sub1:sgpr_96 = COPY undef %0:sgpr_32 %3:vgpr_32 = V_LSHL_ADD_U32_e64 %1.sub1:sgpr_96, ... GCNRewritePartialRegUses produced: %4:vgpr_32 = COPY undef %1:sgpr_32 dead %2:vgpr_32 = V_LSHL_ADD_U32_e64 %4, ... Register class for %4 is incorrect: there should be sgpr_32 instead of vgpr_32 because the original %1 had scalar regclass. This patch fixes that. Note that GCNRewritePartialRegUses pass isn't enabled by default yet.