llvm-project

698cd48d - [RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext (#136287)

[RISCV] Fix Lsb > Msb case in (sra (sext_inreg X, _), C) for th.ext (#136287) According the [spec](https://github.com/XUANTIE-RV/thead-extension-spec/releases/tag/2.3.0), the operation of `th.ext rd, rs1, msb, lsb` is reg[rd] := sign_extend(reg[rs1][msb:lsb]) The spec doesn't specify if lsb is greater than msb. I don't think lsb can be greater than msb. So that If the shift-right amount is greater than msb, we can set lsb equal to msb to extract the bit rs1[msb] and sign-extend it.