llvm-project

6993d32c - [Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419)

[Exegesis][RISCV] Add RISCV support for llvm-exegesis (#120419) This patch also makes following amendments to core exegesis: * Added distinction between regular registers aliasing check and registers used as memory address in instruction. * Added scratch memory space pointer register. * General exegesis options were amended: * mattr - new option to pass a list of enabled target features Llvm-exegesis RISCV port is a result of team effort. Below everyone involved listed. Co-authored-by: Konstantin Vladimirov <konstantin.vladimirov@syntacore.com> Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com> Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com> Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com> Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com> --------- Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>