[AMDGPU] Add heuristic to set CarriedLatencies (#224057)
After
https://github.com/llvm/llvm-project/commit/8723e4a1bc0b6078e35c17532952f79fb8480f53
users have some control to defer scheduling instructions which depend on
loads from predecessor blocks. This PR adds a simple heuristic to
control setting the Fence mode, which has shown to be the most useful in
practice.
We would like to defer scheduling the ATOMIC_FENCE, if 1. there is a
corresponding load/store in flight, and 2. there have not been enough
cycles for that instruction to reasonably finish. Unfortunately, since
we are reasoning about loads/stores in predecessor blocks, we can not
reliably know where these will in the final schedule. However, we can
inspect the dependency structure to identify cases where these
instructions may be pushed back.
This heuristic identifies predecessor blocks in which ds_loads must be
scheduled after all wmma instructions, as this dependency structure
commonly leads to ds_loads at the end of the block. In such scenarios,
we defer scheduling the fence to attempt to hide latency from incoming
ds_loads.
Users may still override this heuristic as needed, but this heuristic
has shown accuracy for mi450 ML kernels.
