llvm-project

6eae1759 - [RISCV] Remove VMConstraint from VAESKF1_VI/VAESKF2_VI. (#181887)

[RISCV] Remove VMConstraint from VAESKF1_VI/VAESKF2_VI. (#181887) These instructions don't have a VM operand. If these instructions use a V0 destination, the VMConstraint code calls getReg() on the the last operand which is an immediate. This triggers an assertion. Not sure what happens on a release build. It probably treats the immediate as a value in the RISCV register info enum.