llvm-project

7126e6ac - [LLVM][CodeGen][SME] Improve regalloc hinting for multi-vector instructions. (#197711)

[LLVM][CodeGen][SME] Improve regalloc hinting for multi-vector instructions. (#197711) When an instruction uses one of the results of a multi-vector instruction it will typically be a subreg. For it to be considered a suitable reuse candidate we must convert the subreg to its underlying physical register.