llvm-project

75b9b719 - [clang-format] Skip protected data blocks in Verilog (#190695)

[clang-format] Skip protected data blocks in Verilog (#190695) A Verilog file can have encrypted stuff (sections 34 and O in the spec). This patch makes the formatter skip it. Previously the formatter could mess it up by treating it as ordinary code. Now the entire block following the `pragma protect` line is treated as a single token. The keywords added in this patch only mean special things in the pragma lines. Thus they are not added to `VerilogExtraKeywords`. While the files containing the stuff are machine generated, it is a bad idea for a formatter to break code. For example, one may wish to run the formatter on an entire project containing both ordinary and encrypted files. Another use case is formatting the prototypes in files that contain clear text prototypes in and encrypted implementation.