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778dd2c1 - [AArch64][NeoverseV1] Load/Store Register Half with scaling (#222282)

[AArch64][NeoverseV1] Load/Store Register Half with scaling (#222282) On Neoverse V1, LDRH/STRH with scaling has a specific execution compared to other LDR/STR. Opcode | Latency | Pipelines ------------------------------------------- Common LDR | 4 | L LDRH with scaling | 5 | I, L Common STR | 1 | L01, D STRH with scaling | 2 | I, L01, D Verified on Neoverse V1 with micro benchmarks and compared all addressing mode variantes. Neoverse V2 is unaffected (confirmed by SOG documentation and microbenchmarks).