llvm-project

7a37be29 - [LoongArch] Lower vector sign extension with VSLLWIL and VEXTH (#234543)

[LoongArch] Lower vector sign extension with VSLLWIL and VEXTH (#234543) vsllwil.{h.b/w.h/d.w} with a zero shift amount sign-extends the low half of the source elements, and vexth.{h.b/w.h/d.w} the high half. The old lowering needed vslti + vilvl for the low half. Although vsllwil has a higher latency and lower throughput than vilvl, it replaces two single-cycle instructions with the same total latency and issue cost, so it saves an instruction. For the custom SIGN_EXTEND legalization, vsllwil + vexth also replaces vslti + vilvl + vilvh and shortens the high-half path. Chaining two vsllwil for a 4x SIGN_EXTEND_VECTOR_INREG would cost more than the alternative, so interleave the source with itself twice with vilvl, which replicates each element across its destination element, and shift the top copy down with vsrai. When only the sign bits are demanded, the vsrai is dropped. When every element being extended is already all-ones or all-zeros, e.g. a comparison result, interleaving the source with itself already yields the sign extension, so use a single vilvl instead of vsllwil and drop the vsrai for a 4x extension. Assisted-by: GLM 5.3