llvm-project

7b9a9aa7 - TableGen: Store super-register class sets as bit vectors (#234798)

TableGen: Store super-register class sets as bit vectors (#234798) extendSuperRegClasses adds the super-register classes of each register class's super-classes to its own, by merging their sets. The sets were DenseSets, so most of the time went to hashing classes that were already present. Store the sets as bit vectors instead, so merging is a bitwise or. They are indexed by a new CreationIndex, since EnumValue isn't assigned until all classes have been inferred. AMDGPU tablegen runs that build the register bank: Gigainstructions Gigacycles CPU seconds Before 700 435 135 After 622 (-11.1%) 381 (-12.5%) 120 (-11.2%) --------- Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>