llvm-project

7d6e72f1 - [RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_ATOMICRMW_ADD (#155972)

[RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_ATOMICRMW_ADD (#155972) RISCV does not provide a native atomic subtract instruction, so this patch lowers `G_ATOMICRMW_SUB` by negating the RHS value and performing an atomic add. The legalization rules in `RISCVLegalizerInfo` are updated accordingly, with libcall fallbacks when `StdExtA` is not available, and intrinsic legalization is extended to support `riscv_masked_atomicrmw_sub`. For example, lowering `%1 = atomicrmw sub ptr %a, i32 1 seq_cst` on riscv32a produces: ``` li a1, -1 amoadd.w.aqrl a0, a1, (a0) ``` On riscv64a, where the RHS type is narrower than XLEN, it currently produces: ``` li a1, 1 neg a1, a1 amoadd.w.aqrl a0, a1, (a0) ``` There is still a constant-folding or InstConbiner gap. For instance, lowering ``` %b = sub i32 %x, %y %1 = atomicrmw sub ptr %a, i32 %b seq_cst ``` generates: ``` subw a1, a1, a2 neg a1, a1 amoadd.w.aqrl a0, a1, (a0) ``` This sequence could be optimized further to eliminate the redundant neg. Addressing this may require improvements in the Combiner or Peephole Optimizer in future work. --------- Co-authored-by: Kane Wang <kanewang95@foxmail.com>