llvm-project

80e7fe89 - [lldb][RISCV] Fix float load and stores in RISC-V emulator (#167490)

[lldb][RISCV] Fix float load and stores in RISC-V emulator (#167490) This patch fixes 2 fundamental problems in emulating `FLW`, `FSW`, `FLD` and `FSD` instructions. 1. Instructions immediate wasn't sign extended 2. Store instructions always wrote for 64 bits to memory Also this patch fixes 2 lldb tests for RISC-V: TestThreadJump.py and TestBreakpointHitCount.py