llvm-project

85e01ff2 - [AArch64] Lower i16/f16 bitcast via vector operations. (#196341)

[AArch64] Lower i16/f16 bitcast via vector operations. (#196341) This removes one of the uses of getTargetExtractSubreg, that creates a Machine Node during DAG lowering. We instead use a scalar_to_vector to convert to a vector and let the extract element legalize to a legal type.