llvm-project

94239b34 - [AMDGPU][GlobalISel] Add RegBankLegalize rules for permlane16/permlanex16 (#187906)

[AMDGPU][GlobalISel] Add RegBankLegalize rules for permlane16/permlanex16 (#187906) Add RegBankLegalize rules for the amdgcn_permlane16 and amdgcn_permlanex16 intrinsics. Both intrinsics are sources of divergence, so only the divergent case is needed: result, old, and src0 map to VGPR, while src1 and src2 are SGPR with ReadFirstLane if divergent. Update the GISEL RUN lines in llvm.amdgcn.permlane.ll and permlane16_opsel.ll to use -new-reg-bank-select, and regenerate check lines. The v8i16 test cases now produce identical SDAG/GISEL output so their checks are unified.