llvm-project

948c4a2f - [AArch64][GlobalISel] Select vector element extract into GPR (#210030)

[AArch64][GlobalISel] Select vector element extract into GPR (#210030) Prototyping a new minimal type-based approach to RegBankSelect (#199040) for compile-time purposes exposed various gaps in instruction selection when not using the existing RegBankSelect pass. These manifested as new fallbacks when compiling the IR dataset from [1]. This patch teaches instruction selection to handle extracts of scalar i8/i16/i32 into GPR directly. This will prevent new fallbacks being introduced when a new type-based RBS pass is added. The test cases are extracted from [1]. Assisted-by: codex [1] https://davemgreen.github.io/gisel.html