llvm-project

977c516c - [AArch64][llvm] Add GICv5 ICH_PPI_HVIR{0,1}_EL2 system registers (#191818)

[AArch64][llvm] Add GICv5 ICH_PPI_HVIR{0,1}_EL2 system registers (#191818) Add GICv5 `ICH_PPI_HVIR{0,1}_EL2` system registers (Interrupt Controller PPI Hide Virtual Interrupt Registers). These registers are added because a hypervisor may want to only expose a subset of the PPIs to the virtual machine and hide the remaining PPIs. The only way the hypervisor can do this is by trapping all the PPI ICV registers which leads to additional code complexity and adds performance overhead especially for nested virtualization. These are documented here: https://developer.arm.com/documentation/111107/latest/AArch64-Registers/ICH-PPI-HVIR-n--EL2--Interrupt-Controller-PPI-Hide-Virtual-Interrupt-Registers