llvm-project

9bb29c3d - [RISCV][VLOPT] Add support for bitwise logical, single width shift, and vector move (#119412)

[RISCV][VLOPT] Add support for bitwise logical, single width shift, and vector move (#119412) Add support and tests for these instructions. Get operand info test exist in llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir