llvm-project

9ca7d24d - [mlir][vector] Allow signless integer element types in `vector.step` (#205142)

[mlir][vector] Allow signless integer element types in `vector.step` (#205142) `vector.step` previously produced only `index` vectors. Allow its result element type to also be a signless integer of at least 8 bits. If a lane's value in the sequence is not representable in the element type it wraps around (the value is truncated to the element bitwidth), consistent with the [`llvm.stepvector`](https://llvm.org/docs/LangRef.html#llvm-stepvector-intrinsic) intrinsic that `vector.step` lowers to. ConvertVectorToLLVM now lowers `vector.step` to `llvm.intr.stepvector` for all vector types (fixed-width and scalable) rather than materializing an `arith.constant` for fixed-width vectors; the constant form does not make sense at the LLVM boundary, where the intrinsic already carries the target index bitwidth. The in-dialect `arith.constant` lowering remains for other pipelines and is exposed through a new `transform.apply_patterns.vector.lower_step` op. `populateVectorStepLoweringPatterns` takes an `indexBitwidth` used to materialize `index`-typed steps (default 64, preserving existing behavior; 0 leaves them untouched). Integer range inference and the VectorToSPIRV lowering are likewise updated for the new element types and wrap-around. The wrap-around path has no SPIR-V test: SPIR-V vector types are limited to at most a handful of elements, so no legal SPIR-V vector is large enough to exceed an 8-bit (or wider) element range. --- **Note**: AI used to generate the code in this PR. Signed-off-by: Víctor Pérez Carrasco <victorperez@fb.com>