llvm-project

9e5165bd - [LoongArch] Use XVPERMI.Q for lane-crossing LASX shuffles (#232209)

[LoongArch] Use XVPERMI.Q for lane-crossing LASX shuffles (#232209) Introduce XVPERMI.Q ISD node in TableGen for add lowering for 256-bit lane shuffle. Also extend lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle to support dual input permute and shuffle, so that splice like this: ``` %2 = shufflevector <8 x i32> %0, <8 x i32> %1, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14> ``` could be lowered to: ``` (XVBSLL_V $xr2, $xr1, 4) (XVPERMI_Q $xr1, $xr0, 33) (XVBSRL_V $xr0, $xr1, 12) (XVOR_V $xr0, $xr2, $xr0) ``` All permute that destination lane comes from maximum of two source lanes were supported (e.g. 7, 8, 9, 10 comes from V1's higher lane and V2's lower lane), for source lane larger than 3, we could follow X86's `lowerShuffleAsDecomposedShuffleMerge` and `lowerShuffleAsSplitOrBlend` in future patch series.