llvm-project

9fba20bf - [SiFive][RISCV] Remove VMConstraint from XSfvqmaccqoq and XSfvfwmaccqqq instructions. (#142914)

[SiFive][RISCV] Remove VMConstraint from XSfvqmaccqoq and XSfvfwmaccqqq instructions. (#142914) These instructions don't have a mask operand. The VMConstraint would cause an assertion if V0 is used as the destination and the last register isn't V0.