[RISCV][MC] Add experimental `Zvvmm` MC support (#193956)
Add initial MC-layer support for `Zvvmm` from the experimental [RISC-V
Integrated Matrix
Extension](https://github.com/riscv/integrated-matrix-extension/blob/d2e64b4922f5c2c416761f3c7c997d4f0cf814d9/src/integrated-matrix.adoc)
(version
[2026-04-23](https://github.com/riscv/integrated-matrix-extension/releases/tag/riscv-isa-release-d2e64b4-2026-04-23))
This patch:
- Adds the experimental `zvvmm` 0.1 extension feature, depending on
`zve32x`.
- Adds assembler/disassembler definitions for the integer matrix
multiply-accumulate instructions:
- `vmmacc.vv`
- `vwmmacc.vv`
- `vqmmacc.vv`
- `v8wmmacc.vv`
- Adds IME vtype helper modeling in `RISCVVType`, covering lambda
encoding/decoding, IME vtype field masks,
alt format fields, and block-size field handling.
- Adds MC tests for encoding, disassembly, missing-feature diagnostics,
invalid masked forms
- Does not add LLVM IR codegen or clang intrinsic support yet.
