llvm-project

ad810c18 - [X86] Improve PDEP/PEXT instructions scheduling on znver1/znver2 models (#217304)

[X86] Improve PDEP/PEXT instructions scheduling on znver1/znver2 models (#217304) znver1/znver2 have notoriously bad implementations of the PDEP/PEXT scalar instructions, just using the WriteMicrocoded tag isn't useful as it can't give any indication of the awful effect on ALU pipes or uops flooding. The measurements on uops.info/Agner are all over the place (and are very input dependent), so I've taken an average of the worse case to at least give the scheduler something to work with. We've ignored these so far, but now we're close to generating llvm.pdep/pext intrinsics (and scalarizing vector implementations).