llvm-project

ada3f57b - [WebAssembly][FastISel] Fix sext i1 to i64 with +sign-ext (#213734) (#214007)

[WebAssembly][FastISel] Fix sext i1 to i64 with +sign-ext (#213734) (#214007) Fixes #213734 --- ## Summary At `-O0`, WebAssembly FastISel could miscompile programs that sign-extend an i1 value to i64 when the `+sign-ext` target feature is enabled. The bug was introduced in LLVM 23 by the FastISel sign-ext optimization (#179855). For `sext i1 to i64`, FastISel fell through its switch without emitting any instruction and returned an undefined register. Code that uses this pattern to adjust integer division results (such as floor division) could then compute the wrong answer. The issue reporter saw `-1` instead of the correct `-2`. This patch restructures `signExtend()` so i8, i16, and i32 still use their native WebAssembly sign-extension instructions, while i1 goes through the existing generic path: sign-extend in i32 via shifts, then `i64.extend_i32_s`. ## Test plan - [x] Added `i64_extend1_s` to `signext-inreg.ll` (covers FastISel and DAG, with and without `+sign-ext`) - [x] Verified issue repro: `llc repro.ll -O0` now returns `-2` (was `-1`); `--fast-isel=false` still returns `-2` - [x] `./bin/llvm-lit -j1 ../llvm/test/CodeGen/WebAssembly` <img width="3072" height="1920" alt="image" src="https://github.com/user-attachments/assets/0944887b-54b8-4e8d-8291-a64b03ff3786" /> --------- Signed-off-by: Gaurav Chaudhary <chaudharygaurav2004@gmail.com>