llvm-project

aee55a87 - [X86] combineMinMaxReduction - match any minmax reduction to a legal scalar (#195261)

[X86] combineMinMaxReduction - match any minmax reduction to a legal scalar (#195261) Further relaxation of the VECREDUCE minmax folds - recognise any >=128-bit vector that reduces to a legal scalar. Adds custom ops for more VECREDUCE types (inc vXi32/vXi64 types) Remaining issues are sub-128-bit vector reductions (unnecessary padding with neutral elements) and handling of i64 types on 32-bit targets - I'm working on fixes for both of these.