llvm-project

b2837fae - [AMDGPU] Add tests for misaligned AGPR tuples in memory-op operands, NFC (#236205)

[AMDGPU] Add tests for misaligned AGPR tuples in memory-op operands, NFC (#236205) Pre-commit test: on gfx90a, misaligned AGPR tuples in DS/FLAT/global atomics are currently rejected by the generic validateVGPRAlign scan ("invalid register class: vgpr tuples must be 64 bit aligned"), unlike their VGPR counterparts which are rejected by the operand register class ("invalid operand for instruction"). A following change routes the AGPR memory-op operands through the aligned operand class to match. --------- Co-authored-by: Claude <noreply@anthropic.com>