llvm-project

b830bcfd - [AMDGPU]Fix compute num sign bits unsigned underflow (#182723)

[AMDGPU]Fix compute num sign bits unsigned underflow (#182723) Fixes #182677 The `BFE_I32` case in `ComputeNumSignBitsForTargetNode` was not masking the width operand with `& 0x1f`, unlike other BFE operations in the same file. Since the hardware instruction only uses the low 5 bits of the width field, values >= 32 passed via `@llvm.amdgcn.sbfe.i32` caused unsigned integer underflow in the calculation: unsigned SignBits = 32 - Width->getZExtValue() + 1; When width > 33, this underflows, producing incorrect SignBits values. When width == 33, SignBits becomes 0, violating the expected return range of [1, BitWidth]. This led to assertion failures and miscompilation where subsequent BFE narrowing operations were incorrectly eliminated. This patch: - Masks the width value with `& 0x1f` to match hardware behavior - Handles width == 0 (after masking) by returning 32 sign bits - Adds regression tests for width values >= 32