llvm-project

b966c71b - [AMDGPU] Fix true16 high-half packing when the low operand is not a VGPR (#220843)

[AMDGPU] Fix true16 high-half packing when the low operand is not a VGPR (#220843) The true16 (hi << 16) | z pattern used v_or_b16 and EXTRACT_SUBREG hi16 on z. That is only valid when z is a VGPR. When z is an immediate (e.g. 0x3c00), EXTRACT_SUBREG hi16 does not isolate the high 16 bits, so the whole constant is ORed into hi: we get (hi | 0x3c00) << 16 instead of hi << 16. Select v_lshl_or_b32 instead, with z as VSrc_b32, matching the fake16 path.