llvm-project

bd1561d5 - [RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995)

[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995) GISel doesn't distinquish integer and FP loads and stores. We only know which it is after register bank selection. This results in s16/s32 loads/stores on the GPR register bank that need to be selected. This required extra isel patterns not needed for SDAG and adding i16 and i32 to the GPR register class. Having i16/i32 on the GPR register class makes type interfence in tablegen less effective, requiring explicit casts to be added to patterns. It also increases the size of RISCVGenDAGISel.inc by 2K. This patch removes the extra isel patterns and replaces it with custom instruction selection similar to what is done on AArch64. A future patch will remove i16 and i32 from the GPR register class.